The Satellite System allows for the creation and use of a supporting CPLD, termed a Sidekick. The Chocolate board includes a MAX V CPLD running the Rascal image.
A CPLD, amongst other things, allows efficient parallel routing of signals between sets of inputs and outputs, along with the application of logic to those signals. Unlike a microcontroller (MCU), which generally works by executing sequential sets of instructions, a CPLD processes incoming and outgoing logic in parallel according to the logic that has been programmed onto the device.
A CPLD has a number of resources that are available that determine the complexity of the logic routing on the device. For a MAX V CPLD, one of these resources are Logic Elements (LEs). Logic elements are essentially on-device modules that can perform certain logic and register operations. Programs (generally written in VHDL or Verilog) are mapped to the LEs in a way that makes efficient use of them for that device. More complex operations require greater numbers of LEs to implement. Higher-end devices in the same family tend to have more LEs available, allowing more complex programs to be written to them.
Replacing the logic on the device requires the device to be flashed, and similarly to MCUs there is a limit as to how many times this may be done before the process becomes unreliable. The limit is usually much lower on CPLDs than on MCUs, so care should be taken as to how many times an image is flashed. For example, the MAX V CPLD is rated for only 100 flashes. In practice you will likely get many more, but there will be a point at which it will become impossible to perform a successful flash.
The Rascal image manages routing between the MCU, board components, and external pins. The Rascal image is a single image requiring a single flash, but is designed in such a way that the MCU can communicate with it and request certain fixed configuration changes. For example, the RGB LEDs can be configured to be either controllable by three MCU signals, fifteen MCU signals, or disabled entirely. If you wished to add further configuration options, then you would need to add further functionality to the image, which would require flashing the device with that new image.
On the Chocolate board, 37 general-purpose lines are connected directly between the MCU and CPLD and to a header pin. These can be used for direct communication, or disabled on one side and used with a header instead. IN addition, there are ten lines available that are directly connected between a header and the CPLD.
The means of creating CPLD images in the Satellite System is still very simple and very much in flux. You can create images using a configuration file. This will be converted into VHDL code that can be fed into another tool to build the actual image. You do not need to know VHDL to create a CPLD image using the Satellite System, but it helps. You can optionally mix VHDL code into the code generated by the Satellite System.
Following is a simple example that creates a 2-bit register that if used to select the input for for an RGB LED on the Chocolate board:
!memory a m_led 2 !operations m m_led led(3) axi(I_PC0);axi(I_PC23);0;1 m m_led led(4) axi(I_PC1);axi(I_PC24);0;1 m m_led led(5) axi(I_PC2);axi(I_PC26);0;1
This code assigns a 2-bit memory location called
m_led, initially set to zero, that can be configured over SPI. The current value of
m_led will be used to select an output for the
led(3-5) outputs. These outputs are connected to the controls for LED1 R,G,B on the Chocolate board. The values output on
led(3-5) will be as follows:
m_ledis 0, the values read on the PC0-2 lines coming in from the MCU will be used.
m_ledis 1, the values read on the PC23-24 and PC26 lines from the MCU will be used.
m_ledis 2, a logic zero will be used. This will turn off the LED.
m_ledis 3, a logic one will be used. This will turn on the LED at full brightness.